Low density parity check codes are used in storage applications, including flash memory based storage controllers. Low density parity check decoders provides capability of soft decision decoding, which improves error rate performance compared to hard decision decoding. However, compared to conventional algebraic error correcting code schemes, low density parity check codes suffer from error floors which are known to be caused by trapping sets (near codewords) under commonly used iterative decoding algorithms. The error floor can be lowered by carefully reducing the number of harmful trapping sets in code construction.
In flash memory, defects (more generally hard errors) can trigger such trapping sets with much higher probability than in additive white Gaussian noise channels. Such hard errors leads to log-likelihood ratios that are saturated or almost saturated in the wrong direction (i.e., the sign of the log-likelihood ratio is wrong), which probabilistically triggers trapper sets in iterative decoding.
Consequently, it would be advantageous if an apparatus existed that is suitable for correcting or compensating for hard errors in low-density parity check decoding.